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A bit-serial architecture for a multiplierless DCT

Choomchuay, S. and Timakul, S. (2003) A bit-serial architecture for a multiplierless DCT. Journal of ICT, 2 (1). pp. 15-30. ISSN 1675-414X

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Official URL: http://jict.uum.edu.my


This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to a 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For low power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. Varying data word length, MSE obtained form our approach and some similar algorithms are also investigated and reported.

Item Type: Article
Uncontrolled Keywords: DCT, multiplierless DCT, BinDCT, VLSI image coding
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Depositing User: Mrs. Norazmilah Yaakub
Date Deposited: 05 Sep 2010 07:27
Last Modified: 05 Sep 2010 07:27
URI: http://repo.uum.edu.my/id/eprint/1019

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