Mohd Fazil, Azlan Faizal and Mohd Shaharanee, Izwan Nizal and Mohd Jamil, Jastini and Ang, Jin Sheng (2020) Framework to reduce cost scrapping and cost of assemble test capacity in semiconductor integrated circuit manufacturing. Technology Reports of Kansai University, 62 (7). pp. 3625-3630. ISSN 04532198

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Abstract

Semiconductor including integrated circuit (IC) is an expensive and complicated process. The trend of semiconductor packaging is going towards better performance with lower power consumption packages. Thus, the single-die packaging trend has evolved into multi-die packaging. The evolution of multi-die packaging requires more tools and processing steps in the assembly process. Furthermore, any die is tested at Class, and detected faulty will cause the whole package to be scrapped. These factors cause a bigger loss in production yield to compare to the single-die packaging. A new framework is suggested for model training and evaluation for the application of machine learning in the semiconductor test. The proposed new framework will be able to provide a range of possible recall rates from minimum to maximum to identify which machine learning algorithms specifically.

Item Type:	Article
Uncontrolled Keywords:	Machine Learning, Integrated Circuit, Semiconductor, Predictive Modelling.
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions:	School of Quantitative Sciences
Depositing User:	Mrs. Norazmilah Yaakub
Date Deposited:	07 Feb 2021 05:31
Last Modified:	07 Feb 2021 05:31
URI:	https://repo.uum.edu.my/id/eprint/28159

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