Razak, Abdul Hadi Abdul and Zaharin, Muhamad Iqbal Abu and Haron, Nor Zaidi (2007) Implementing digital finite impulse response filter using FPGA. In: Asia-Pacific Conference on Applied Electromagnetics, 2007 (APACE 2007), 4-6 Dec. 2007 , Kuala Lumpur.

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Abstract

This paper describes the design of Transposed Form FIR filter implemented in the Spartan-II and Virtex-E family of FPGAs. The design is an 8-tap filter based on 16-bit input samples and 14-bit signed coefficients.The basic building blocks of the filter are KCMs, Adders, Registers, and a delay-locked loop.All the 14-bit coefficient factors are stored with an 18-bit word size in the ROM.The program is written in VHDL source code based on application Xilinx notes [1] that describe the design of an FIR filter.The software tools have been used are Xilinx ISE Webpack 8.1, ModelSim 6.1e and Matlab 7.0.

Item Type:	Conference or Workshop Item (Paper)
Additional Information:	Print ISBN: 978-1-4244-1434-5
Uncontrolled Keywords:	FIR Filter, FPGA, Matlab, VHDL, Xilinx.
Subjects:	Q Science > QA Mathematics > QA76 Computer software
Divisions:	College of Arts and Sciences
Depositing User:	Mr. Abd Hadi Abd Razak
Date Deposited:	27 May 2013 04:19
Last Modified:	27 May 2013 04:19
URI:	https://repo.uum.edu.my/id/eprint/4561

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